(a) Field of the Invention
The present invention relates to semiconductor device having a test circuit for testing an output circuit thereof, and a method for testing the output circuit of a semiconductor device.
(b) Description of the Related Art
A semiconductor device such as IC or LSI having therein output circuits, e.g. buffer circuits, is subjected to a characteristic test wherein the resistance of the output terminal (external terminal) of the output circuit is measured. In the characteristic test, after the output circuit is applied with a power source voltage from the tester via a probe or socket, the output voltage on the external terminal is measured, and the resistance of the external terminal is obtained therefrom. Since an especially higher accuracy is requested in the measurement of the resistance for the output circuit nowadays, it is improper to neglect the contact resistance on the external terminal caused by the probe or socket as well as the resistance of the tester itself during the voltage measurement.
Patent Publication JP-A-2000-214225 describes a technique for improving the accuracy in the characteristic test, wherein dedicated test terminals are used for the characteristic test. FIG. 7 shows the test circuit described in the publication. In the semiconductor device 200, if a specified combination of signals is applied through input terminals P1 to P3, a decoder 202 delivers a first control signal C1, based on which a control circuit 203 turns ON a bipolar transistor 205, for example, whereby bipolar transistor 205 is subjected to the characteristic test.
In the characteristic test of bipolar transistor 205, a power source terminal P4 is connected to a test power source (battery) B1, an output terminal is connected to a measurement load L1, and a sense terminal P10 is connected to a voltmeter Vt3. A current I0 flows from the battery B1 through power source terminal P4, bipolar transistor 205, output terminal P6 and the measurement load L1. In this state, decoder 202 delivers a second control signal C2, to turn ON a first switch SW1 for a specified time interval, whereby voltmeter Vt3 connected to the sense terminal P10 indicates the voltage Va on the emitter of bipolar transistor 205 (or source terminal P4). Subsequently, a third switch SW3 is turned ON for a specified time interval, whereby voltmeter Vt3 connected to the sense terminal P10 indicates the voltage Vb on the collector of bipolar transistor 205 (or output terminal P6).
Current I0 supplied from the battery B1 is also measured, and the ON-resistance of bipolar transistor 205 is obtained based on current I0 and voltages Va and Vb thus measured. In the described technique, either the potential of the power source terminal P4 or the output terminal P6 is delivered through the sense terminal P10 by selectively turning ON the first switch SW1 or the third switch SW3. By delivering the potential of the power source terminal P4 or the output terminal P6, the emitter-to-collector voltage drop Von of bipolar transistor 205 can be obtained while substantially removing the influence by the contact resistance involved by the connection of the measurement load L1 to the output terminal P6.
In the technique described in JP-A-2000-214225, however, the dedicated test terminals provided for the semiconductor device significantly increases the dimensions of the semiconductor device.
JP-A-11-30649 describes another technique for improving the accuracy in the characteristic test of the semiconductor device, wherein the characteristic of the semiconductor device is measured without connecting the output terminal to the measurement load. FIG. 8 shows the circuit diagram during the characteristic test described therein. In the characteristic test of the semiconductor device 300, a control circuit 306 controls to turn ON both first and second transistors 301 and 302, thereby flowing a penetrating current through transistors 301 and 302.
The potential of the output terminal 309 connected to an intermediate node 310 connecting the source-drain paths of transistors 301 and 302 together is measured, and the source-to-drain voltage drops of transistors 301 and 302 are obtained based on the potential difference between the output terminal 309 and the power source terminal 303 and the potential difference between the output terminal 309 and the ground terminal 304, respectively. The characteristic of the semiconductor device 300 is obtained based on the relationship between the source-to-drain voltage drop of each transistor 301 and 302 and the current value of the penetrating current flowing from the power source terminal 303 to the ground terminal 304 through the first and second transistors 301 and 302.
In the technique described in JP-A-11-30649, the influence by the contact resistances involved with the power source terminal 303 and the ground terminal 304 is alleviated by the configuration wherein a large number of terminal pins are provided for each of the power source terminal 303 and the ground terminal 304 and are contacted by the respective probe pins connected in parallel.
However, this technique is limited to the case wherein a large number of terminal pins are provided for the power source terminals and the ground terminals, and if a smaller number of terminal pins are provided for the power source terminal or ground terminal, the influence by the contact resistances cannot be effectively removed.